IBIS Macromodel Task Group

Meeting date: 24 September 2013

Members (asterisk for those attending):
Agilent:                      Fangyi Rao
                              Radek Biernacki
Altera:                     * David Banas
                              Julia Liu
                              Hazlina Ramly
Andrew Joy Consulting:        Andy Joy
ANSYS:                        Samuel Mertens
                            * Dan Dvorscak
                            * Curtis Clark
                              Steve Pytel
                              Luis Armenta
Arrow Electronics:            Ian Dodd
Cadence Design Systems:       Terry Jernberg
                            * Ambrish Varma
                              Feras Al-Hawari
                            * Brad Brim
                              Kumar Keshavan
                              Ken Willis
Cavium Networks:              Johann Nittmann
Celsionix:                    Kellee Crisafulli
Cisco Systems:                Ashwin Vasudevan
                              Syed Huq
Ericsson:                     Anders Ekholm
IBM:                          Greg Edlund
Intel:                        Michael Mirmak
Maxim Integrated Products:    Mahbubul Bari
                              Hassan Rafat
                              Ron Olisar
Mentor Graphics:            * John Angulo
                              Zhen Mu
                            * Arpad Muranyi
                              Vladimir Dmitriev-Zdorov
Micron Technology:          * Randy Wolff
                            * Justin Butterfield
NetLogic Microsystems:        Ryan Couts
Nokia-Siemens Networks:       Eckhard Lenski
QLogic Corp.                  James Zhou
SiSoft:                     * Walter Katz
                              Todd Westerhoff
                              Doug Burns
                            * Mike LaBonte
Snowbush IP:                  Marcus Van Ierssel
ST Micro:                     Syed Sadeghi
Teraspeed Consulting Group:   Scott McMorrow
                            * Bob Ross
TI:                           Casey Morrison
                              Alfred Chong
Vitesse Semiconductor:        Eric Sweetman
Xilinx:                       Mustansir Fanaswalla
                              Ray Anderson

The meeting was led by Arpad Muranyi

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Opens:

- None

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Call for patent disclosure:

- None

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Review of ARs:

- Arpad send Package Modeling Decisions presentation to Mike for posting
  - Done

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New Discussion:

Interconnect Task Group report:

Arpad said there was no meeting last week. The group remains dormant.


Discussion of on-die and package modeling proposals:

Walter showed a presentation on on-die and package modeling using EMD,
starting at slide 7.  He described the various EMD syntax examples within.
On slide 11 John noted that on a DRAM there would be more pins than shown.
Walter said the example was reduced for simplicity, and that vendors
have a choice as to how they group pins for analysis.  On slide 12
Walter noted that ground pins were not included along with power, based
on feedback from Randy.  Brad asked if the "Victim" and "Aggressor" fields
used to be "Connection". Walter explained that Connection applies where all
pins can be both aggressor and victim.

On slide 14 Walter noted that one-to-one correspondence is assumed from
die pads to pins.  Slide 15 addresses how to handle the case where this
is not true.

On slide 17 John said there is not enough information to convey stronger
and weaker aggressors. Also where there is one aggressor it is not known
which pin it is. In post-layout a tool might get different results on
successive runs if it makes different choices. This is a result of trying
to use limited models.  Bob said this is an IC vendor issue.  Walter said
that full models are needed for accuracy, and tools are now available to
create those.  Arpad felt that slide 17 did not reflect a comment from
John last week, in which he suggested that a full model can be created
with BIRD 125, but the s-parameters would not have to be full. No sliding
algorithm would be needed, the tool could find the pins to associate with
a sparse matrix.  John said he had misspoken about Touchstone 2.0 last
week, Touchstone 2.1 is needed for sparse matrix format.  Arpad said
that did not make it into the Touchstone 2.1 spec.

Walter noted on slide 18 that Scott McMorrow had asked for a FEXT/NEXT
identification.  Slides 19 and 20 showed two proposals for handling that.

Brad noted that a slide said that how to handle aggressors was "open
for discussion".  Walter suggested that another way to handle aggressors
is to scale them. There are multiple ways to do this, and IC vendors
would have to express their preference. He also said BIRD 125 would not
be able to do this.  Brad asked if EDA tools would be able to use the
information deterministically, or if user guidance would be required.
Walter said the proposal would at least standardize models so that
manual wrapping and import would not be required. He invited IC vendors
to express how they would like to handle this?  Randy said the FEXT/NEXT
methodology is not something he has used before, but it might be useful.
Walter was not sure the FEXT/NEXT concept should be in IBIS.

Arpad said that slide 14 seemed to conflict with Walter's earlier
statement that EMD was for modules, not on-die or packages.  Walter said
that could be handled with an IBIS keyword approach instead of parameter
trees.  Arpad asked how the case 5 example he wrote using BIRD 125
would work with Walter's proposal.  Walter said associations could be
made either through pins or models.  Arpad said that BIRD 125 could do
that too.  Walter felt that BIRD 125 would be more complicated while
offering no more functionality, and that a full implementation example
would show that. He suggested that a BIRD 125 example of cases show
today should be shown next week.

AR: Walter send on-die and package modeling presentation to Mike for posting

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IBIS Interconnect SPICE Wish List:

1) Simulator directives
